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Published Online:pp 50-64https://doi.org/10.1504/IJES.2005.008808

In recent years there has been significant interest in the area of Hardware-based Genetic Algorithms (HGA) implemented using a Field Programmable Gate Array (FPGA). This paper presents a hardware-based genetic optimiser applied to adjusting an adaptive antennae receiver. The proposed architecture employs a combination of pipelining and parallelisation to achieve significant speedups over software implementation. The proposed HGA is implemented on a prototyping board with a Xilinx Virtex-E FPGA and reaches a speedup factor of more than 500 when compared to the software implementation.

Keywords

hardware-based genetic algorithms, adaptive antennae arrays, field programmable gate arrays, FPGA, smart antennae receivers, pipelining, parallelisation, speedups, genetic optimiser, embedded systems